1. Field of the Invention
The present invention is generally in the field of semiconductor chip packaging. More specifically, the present invention is in the field of leadless chip carrier design and structure.
2. Background Art
The semiconductor fabrication industry is continually faced with a demand for smaller and more complex dies. These smaller and more complex dies must also run at higher frequencies. The requirement of smaller, more complex, and faster devices has resulted in new challenges not only in the fabrication of the die itself, but also in the manufacturing of various packages, structures, or carriers that are used to house the die and provide electrical connection to “off-chip” devices.
As an example, the demand for higher frequencies means, among other things, that “on-chip” and “off-chip” parasitics must be minimized. For example, parasitic inductance, capacitance, and resistance, which all adversely affect electrical performance of the die and its associated off-chip components must be minimized. Since RF (“Radio Frequency”) semiconductor devices run at high frequencies, those devices (i.e. RF devices) constitute a significant category of devices that specially require very low parasitics.
Recently, surface mount chips and chip carriers have gained popularity relative to discrete semiconductor packages. A discrete semiconductor package typically has a large number of “pins” which may require a relatively large space, also referred to as the “footprint,” to mount and electrically connect the discrete semiconductor package to a printed circuit board. Moreover, the cost and time associated with the manufacturing of the discrete semiconductor package and the cost and time associated with drilling a large number of holes in the printed circuit board are among additional reasons why alternatives such as surface mount devices and chip carriers have gained popularity.
There have been various attempts in the art to arrive at different chip carrier designs. Japanese Publication Number 10313071, published Nov. 24, 1998, titled “Electronic Part and Wiring Board Device,” on which Minami Masumi is named an inventor, discloses a structure in which to dissipate heat emitted by a semiconductor device. The structure provides metallic packed through-holes formed in a wiring board that transmit heat emitted from a bare chip through a heat dissipation pattern on the bottom of the wiring board, and then to a heat dissipation plate.
Japanese Publication Number 02058358, published Feb. 27, 1990, titled “Substrate for Mounting Electronic Component,” on which Fujikawa Osamu is named an inventor, discloses a substrate with a center area comprising eight thermally conductive resin-filled holes sandwiched between metal-plated top and bottom surfaces. An electronic component is then attached to the center area of the top metal-plated surface of the substrate with silver paste adhesive to improve heat dissipation and moisture resistance. Japanese Publication Number 09153679, published Jun. 10, 1997, titled “Stacked Glass Ceramic Circuit Board,” on which Miyanishi Kenji is named an inventor, discloses a stacked glass ceramic circuit board comprising seven stacked glass ceramic layers. The multi-layer stacked glass ceramic circuit board further comprises a number of via holes comprising gold or copper with surface conductors on the top and bottom surfaces covering the via holes. The top conductor functions as a heat sink for an IC chip.
Japanese Publication Number 10335521, published Dec. 18, 1998, titled “Semiconductor Device,” on which Yoshida Kazuo is named an inventor, discloses a thermal via formed in a ceramic substrate, with a semiconductor chip mounted above the thermal via. The upper part of the hole of the thermal via is formed in a ceramic substrate in such a manner that it becomes shallower as it goes outward in a radial direction.
A conventional chip carrier structure for mounting a chip on a printed circuit board has a number of shortcomings. For example, conventional chip carriers still introduce too much parasitics and still do not provide a low inductance and resistance ground connection to the die. Conventional chip carriers also have a very limited heat dissipation capability and suffer from the concomitant reliability problems resulting from poor heat dissipation. As an example, in high frequency applications, such as in RF applications, several watts of power are generated by a single die. Since the semiconductor die and the chip carrier are made from different materials, each having a different coefficient of thermal expansion, they will react differently to the heat generated by the die. The resulting thermal stresses can cause cracking or a separation of the die from the chip carrier and, as such, can result in electrical and mechanical failures. Successful dissipation of heat is thus important and requires a novel structure and method.
The demand for smaller and more complex dies, together with the demands for higher performance and lower cost, have additionally challenged the semiconductor fabrication industry to provide new levels of system integration. For example, the merging of computer technology with telecommunications has challenged the semiconductor fabrication industry to integrate two different technologies, i.e. analog RF technology, and digital technology, on the same chip. However, combining two different technologies, such as analog RF technology, and digital technology, on the same chip presents difficulties. For example, noisy digital circuits are difficult to integrate with noise-sensitive analog circuits.
In order to overcome the problems of combining two different technologies, such as the analog RF technology and the digital technology, two or more separate dies, instead of a single die, are housed and interconnected in the same package. There are also other reasons for housing two or more dies in the same package. For example, housing two dies in the same package enables the two dies to be interconnected by directly wire bonding of the semiconductor die signal bond pads on a first die to the semiconductor die signal bond pads on a second die. As such, the need for complex interconnect routing is avoided while a relatively short and low parasitic interconnect between the two dies is achieved.
However, the conventional multi-die packages suffer from some of the disadvantages of discrete semiconductor packages and conventional chip carriers discussed above. Thus, there exists a need for a novel and reliable structure and method to support, house, and electrically connect multiple semiconductor dies to a printed circuit board while overcoming the problems faced by discrete semiconductor packages and conventional chip carriers. As such, there is need for a level of system integration that provides for multiple dies housed and interconnected on a printed circuit board while providing low parasitics, efficient heat dissipation, and a low inductance and resistance ground.